{"id":222,"date":"2026-08-19T11:45:54","date_gmt":"2026-08-19T08:45:54","guid":{"rendered":"https:\/\/jkauppa.fi\/?p=222"},"modified":"2026-08-19T11:45:56","modified_gmt":"2026-08-19T08:45:56","slug":"gate-pipeline-compute-circuit","status":"publish","type":"post","link":"https:\/\/jkauppa.fi\/index.php\/2026\/08\/19\/gate-pipeline-compute-circuit\/","title":{"rendered":"MISC K64 Chip"},"content":{"rendered":"\n

MISC compute chip contains 64k cores, and 8TB shared multiport fpga bitwise logic-element register nvsram. Each core contains 8x fully featured 64\/32\/16\/8-bit floating point, integer, and bitwise operations alu’s. Every instruction uses\/operates on full 64-bit register values always, and runs in 1 cycle. Every integer instruction uses two’s complement signed long integer operations. Instruction high bits can contain specific simple variations of instructions, and vector duplicates. Each 64-bit instruction is formed from 16-bit [regX regY regZ insT] parameters. insT parameter is formed from 8-4-4-bit [vecN insV insO] parameters. Estimated logic transistors per core is 1million making 64k cores about 64 billion. Estimated ram transistors per core is 8million 512KB and 512billion total 32GB. Estimated compute 64-bit teraops at 5GHz x 8-vector per core is 40gops and 2560tops total.<\/p>\n\n\n\n

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MISC instruction set architecture:<\/p>\n\n\n\n

Op  | Instruction (-, 32, 16, 8)          | Description (1x64b, 2x32b, 4x16b, 8x8b)\n----------------------------------------------------------------------------------------------------\nany | Raw Data                            | any raw data\n      ## LABEL                              direct data line 64-bit value, or LABEL: address\n0   | Flow Control                        | generic flow control\n      LABEL: nop [] \/\/                      insV=0 sleep regXYZN cycles, halt all-1, LABEL, comment\n      jmpi, jmp, jmpc                       insV=1-3 jump to constant\/LABEL regXYZN, regX, if regY\n      ldi, ld, ld32, ld16, ld8              insV=4-8 load regX constant\/LABEL regYZ, lane 1 regY\n      clk, rnd, core, time                  insV=9-C clock counter, random, core info, nanotime\n      memc                                  insV=D config op vecN ram[regX] ram[regZ] to ram[regY]\n      memr, memw                            insV=E-F load\/store regX from\/to shared ram[regY]\n1   | ALU Compare Zero                    | set 1 if comp regY to zero\n      cmpez, cmpez32, cmpez16, cmpez8       insV=0-3 integer regY equal to zero\n      cmplz, cmplz32, cmplz16, cmplz8       insV=4-7 integer regY less than zero\n      fcmpez, fcmpez32, fcmpez16, fcmpez8   insV=8-B float regY equal to zero\n      fcmplz, fcmplz32, fcmplz16, fcmplz8   insV=C-F float regY less than zero\n2   | ALU Compare Value                   | set 1 if comp regY to regZ\n      cmpe, cmpe32, cmpe16, cmpe8           insV=0-3 integer regY equal to regZ\n      cmpl, cmpl32, cmpl16, cmpl8           insV=4-7 integer regY less than regZ\n      fcmpe, fcmpe32, fcmpe16, fcmpe8       insV=8-B float regY equal to regZ\n      fcmpl, fcmpl32, fcmpl16, fcmpl8       insV=C-F float regY less than regZ\n3   | ALU Compare Special                 | set 1 if comp regY regZ\n      neg, neg32, neg16, neg8               insV=0-3 integer negate\n      copyc, copyc32, copyc16, copyc8       insV=4-7 conditional copy if regZ\n      finf, finf32, finf16, finf8           insV=8-B float is infinity\n      fnan, fnan32, fnan16, fnan8           insV=C-F float is not-a-number\n4   | ALU Bitwise                         | bitwise regY regZ to regX\n      copy, not, or, and                    insV=0-3 bitwise copy\/not\/or\/and\n      nand, nor, xor, xnor                  insV=4-7 bitwise nand\/nor\/xor\/xnor\n      shl, shl32, shl16, shl8               insV=8-B bitwise shift left\n      shr, shr32, shr16, shr8               insV=C-F bitwise shift right\n5   | ALU Bitwise                         | bitwise regY regZ to regX\n      shar, shar32, shar16, shar8           insV=0-3 bitwise arithmetic shift right\n      rotl, rotl32, rotl16, rotl8           insV=4-7 bitwise rotate left\n      rotr, rotr32, rotr16, rotr8           insV=8-B bitwise rotate right\n      ones, ones32, ones16, ones8           insV=C-F bitwise count of one bits\n6   | ALU Bitwise                         | bitwise regY to regX\n      lone, lone32, lone16, lone8           insV=0-3 bitwise lowest one bit or -1 \n      hone, hone32, hone16, hone8           insV=4-7 bitwise highest one bit or -1\n      lzero, lzero32, lzero16, lzero8       insV=8-B bitwise lowest zero bit or -1\n      hzero, hzero32, hzero16, hzero8       insV=C-F bitwise highest zero bit or -1\n7   | ALU Integer                         | integer regY regZ to regX\n      add, add32, add16, add8               insV=0-3 integer add\n      sub, sub32, sub16, sub8               insV=4-7 integer subtract\n      mul, mul32, mul16, mul8               insV=8-B integer multiply\n      div, div32, div16, div8               insV=C-F integer divide\n8   | ALU Integer                         | integer regY regZ to regX\n      addo, addo32, addo16, addo8           insV=0-3 integer add overflow\n      subb, subb32, subb16, subb8           insV=4-7 integer subtract borrow\n      mulo, mulo32, mulo16, mulo8           insV=8-B integer multiply overflow\n      divr, divr32, divr16, divr8           insV=C-F integer divide remainder\n9   | ALU Float                           | float regY regZ to regX\n      fadd, fadd32, fadd16, fadd8           insV=0-3 float add\n      fsub, fsub32, fsub16, fsub8           insV=4-7 float subtract\n      fmul, fmul32, fmul16, fmul8           insV=8-B float multiply\n      fdiv, fdiv32, fdiv16, fdiv8           insV=C-F float divide\nA   | ALU Float                           | float regY regZ to regX\n      fneg, fneg32, fneg16, fneg8           insV=0-3 float negate\n      flog, flog32, flog16, flog8           insV=4-7 float logarithm\n      fpow, fpow32, fpow16, fpow8           insV=8-B float power\n      fsqrt, fsqrt32, fsqrt16, fsqrt8       insV=C-F float square root\nB   | ALU Float                           | float regY regZ to regX\n      fsin, fsin32, fsin16, fsin8           insV=0-3 float sine\n      ftan, ftan32, ftan16, ftan8           insV=4-7 float tangent\n      fcos, fcos32, fcos16, fcos8           insV=8-B float cosine\n      fmin, fmin32, fmin16, fmin8           insV=C-F float min\nC   | ALU Float                           | float regY regZ to regX\n      fasin, fasin32, fasin16, fasin8       insV=0-3 float arcsine\n      fatan, fatan32, fatan16, fatan8       insV=4-7 float arctangent\n      facos, facos32, facos16, facos8       insV=8-B float arccosine\n      fmax, fmax32, fmax16, fmax8           insV=C-F float max\nD   | ALU Float                           | float regY to regX\n      fln, fln32, fln16, fln8               insV=0-3 float natural log\n      fexp, fexp32, fexp16, fexp8           insV=4-7 float exponential\n      fabs, fabs32, fabs16, fabs8           insV=8-B float abs\n      fgam, fgam32, fgam16, fgam8           insV=C-F float gamma(x+1) = n!\nE   | ALU Conversion                      | conversion regY to regX\n      ftin, ftin32, ftin16, ftin8           insV=0-3 float to integer nearest\n      ftid, ftid32, ftid16, ftid8           insV=4-7 float to integer down\n      ftiu, ftiu32, ftiu16, ftiu8           insV=8-B float to integer up\n      ftit, ftit32, ftit16, ftit8           insV=C-F float to integer truncate\nF   | ALU Conversion                      | conversion regY to regX\n      fitf, fitf32, fitf16, fitf8           insV=0-3 integer to float\n      ii32, i32i16, i16i8                   insV=4-6 integer 1x64b->2x32b, 2x32b->4x16b, 4x16b->8x8b\n      i32i, i16i32, i8i16                   insV=7-9 integer 1x32b->1x64b, 2x16b->2x32b, 4x8b->4x16b\n      ff32, f32f16, f16f8                   insV=A-C float 1x64b->2x32b, 2x32b->4x16b, 4x16b->8x8b\n      f32f, f16f32, f8f16                   insV=D-F float 1x32b->1x64b, 2x16b->2x32b, 4x8b->4x16b<\/code><\/pre>\n\n\n\n
Example looping test assembly code source and binary:<\/p>\n\n\n\n
source listing                  | binary           | explanation\n----------------------------------------------------------------------------------------------------\n       ##    0000000000000000   | 0000000000000000 | data lines 0-f\n       []                       | 0000000000000000 | empty line\n       \/\/ empty line            | 0000000000000000 | comment line\nSTART: nop   00000000000200     | 0000000000020000 | sleep for 513 cycles, label START\n       ldi   0000 00000001 ff   | 000000000001FF40 | load registers 0-7 with value 0x1\n       ldi   0008 00000001 ff   | 000800000001FF40 | load registers 8-f with value 0x1\n       ldi   0010 00000000 ff   | 001000000000FF40 | load registers 10-17 with value 0x0\n       ldi   0018 00000000      | 0018000000000040 | load register 18 with value 0x0\n       ldi   0019 00000020      | 0019000000200040 | load register 19 with value 0x20\n       ldi   001a 00000028      | 001A000000280040 | load register 1a with value 0x28\n       ldi   001b 00000001      | 001B000000010040 | load register 1b with value 0x1\n       ldi   001c 00000008      | 001C000000080040 | load register 1c with value 0x8\nCOPY:  copy  0010 0008 0000 ff  | 001000080000FF04 | copy registers 8-f to 10-17, label COPY\n       copy  0008 0000 0000 ff  | 000800000000FF04 | copy registers 0-7 to 8-f\n       add   0000 0008 0010 ff  | 000000080010FF07 | add registers 8-f and 10-17 to 0-7\n       memw  0000 001a 0000 ff  | 0000001A0000FFF0 | write registers 0-7 to mem[28-2f]\n       add   001a 001a 001c     | 001A001A001C0007 | add register 1a and 1c to 1a\n       add   0018 0018 001b     | 00180018001B0007 | add register 18 and 1b to 18\n       sub   001e 0018 0019     | 001E001800190047 | subtract register 18 and 19 to 1e\n       cmplz 001f 001e          | 001F001E00000041 | compare register 1e less 0 to 1f\n       ldi   001d COPY          | 001D0000001B0040 | load register 1d label COPY line number\n       jmpc  001d 001f          | 001D001F00000030 | jump to register 1d if 1f not zero\n       jmpi  START              | 0000000000001210 | jump to label START line number\n       ##    A123456789ABCDEF   | A123456789ABCDEF | data line A123456789ABCDEF<\/code><\/pre>\n\n\n\n
Example looping test assembly to c-code approximate:<\/p>\n\n\n\n
while(true) {                      \/\/ infinite while loop\n  sleep(0x201);                    \/\/ sleep for 513 cycles\n  register<0> long fib1{8} = 0x1;  \/\/ init fib1 with registers array 0-7 to 0x1 vectorized 8x\n  register<8> long fib2{8} = 0x1;  \/\/ init fib2 with registers array 8-15 to 0x1 vectorized 8x\n  register<16> long fib3{8} = 0x0; \/\/ init fib3 with registers array 16-23 to 0x0 vectorized 8x\n  register<24> long i = 0;         \/\/ init loop i with register 24 long integer value 0\n  register<25> long imax = 0x20;   \/\/ init loop imax with register 25 long integer value 0x20\n  register<26> long *mem = 0x28;   \/\/ init mem with register 26 long integer pointer at 0x28\n  for (;i<imax;i++) {              \/\/ for loop long integer i index value from 0 to 31\n    fib3{8} = fib2{8};             \/\/ copy array of old fib2 values to fib3 vectorized 8x\n    fib2{8} = fib1{8};             \/\/ copy array of old fib1 values to fib2 vectorized 8x\n    fib1{8} = fib2{8} + fib3{8};   \/\/ calculate array of new fib1 adding fib2 and fib3 vectorized 8x\n    mem{8} = fib1{8};              \/\/ store array of fib1 values to mem location index vectorized 8x\n    mem += 8;                      \/\/ move memory pointer 8 indexes forward\n  }                                \/\/ for loop close\n}                                  \/\/ infinite while loop close<\/code><\/pre>\n\n\n\n
gate pipeline compute implemented as risc-v compute cores grid routing network. each core has their own 16-bit x 64bit = 512KB internal compute cache, but all middle level memory based caches are replaced with grid routing network for much higher bandwidth. each gate core has 2x 64-bit wide input and 1x 64-bit wide output.<\/p>\n\n\n\n
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gate pipeline compute architecture based on pre-computed nor-memory stored 8-bit values fpga architecture.<\/p>\n\n\n\n
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Logic gate pipeline compute.<\/p>\n\n\n\n
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Logic circuit\/gate assembler.<\/p>\n\n\n\n
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MISC Compute Chip<\/p>\n\n\n\n
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Simultaneous Multiport RAM<\/p>\n\n\n\n
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<\/p>\n","protected":false},"excerpt":{"rendered":"
MISC compute chip contains 64k cores, and 8TB shared multiport fpga bitwise logic-element register nvsram. Each core contains<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[1],"tags":[],"class_list":["post-222","post","type-post","status-publish","format-standard","hentry","category-blog"],"_links":{"self":[{"href":"https:\/\/jkauppa.fi\/index.php\/wp-json\/wp\/v2\/posts\/222","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/jkauppa.fi\/index.php\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/jkauppa.fi\/index.php\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/jkauppa.fi\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/jkauppa.fi\/index.php\/wp-json\/wp\/v2\/comments?post=222"}],"version-history":[{"count":224,"href":"https:\/\/jkauppa.fi\/index.php\/wp-json\/wp\/v2\/posts\/222\/revisions"}],"predecessor-version":[{"id":1177,"href":"https:\/\/jkauppa.fi\/index.php\/wp-json\/wp\/v2\/posts\/222\/revisions\/1177"}],"wp:attachment":[{"href":"https:\/\/jkauppa.fi\/index.php\/wp-json\/wp\/v2\/media?parent=222"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/jkauppa.fi\/index.php\/wp-json\/wp\/v2\/categories?post=222"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/jkauppa.fi\/index.php\/wp-json\/wp\/v2\/tags?post=222"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}